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| Technology family | HC(T) |
| Bits (#) | 8 |
| Supply voltage (min) (V) | 2.8 |
| Supply voltage (max) (V) | 6 |
| IOL (max) (mA | 5.2 |
| IOH (max) (mA) | -5.2 |
| Supply current (max) (µA) | 80 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 125 |
| EM74HC165D | SOP-16L | plastic small outline package; 16 leads; body width 3.9 mm |
| EM74HC165PW | TSSOP-16L | plastic thin shrink small outline package; 16 leads; body width 4.4 mm |
- Wide supply voltage range from 2.8 V to 6.0 V
- High noise immunity
- CMOS low power dissipation
- Asynchronous 8-bit parallel load
- Synchronous serial input
- Latch-up performance exceeds 250 mA
- Complies with JEDEC standard:
- JESD8C(2.8 V to 3.6 V)
- JESD7A(2.8 V to 6.0 V)
- ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V
- CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
The EM74HC165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.